In general, as technology advances, electronic devices become smaller and smaller. At the same time, integrated circuit devices have become increasingly complex and are used in increasing density on integrated circuits within such electronic devices. In some instances, when two circuits are connected, they can be placed side-by-side on a substrate. However, the resulting substrate consumes a significant area. To reduce overall area of a circuit substrate, integrated circuit die are sometimes stacked on top of one another and bonded together by an adhesive to create a multi-chip package.
With stacked die, manufacturing tolerances and fabrication requirements dictate that a second die is placed onto a first die, allowing clearance for bond wires to be connected to bond pads of the first die. Conventionally, such clearance is provided by using a second die that is significantly smaller than the first die, by offsetting the second die relative to a center axis of the first die, by using a mounting structure to elevate the second die relative to the first die, or by rotating the first die by plus or minus 90 or 180 degrees to avoid covering electrical contact structures of the first die.
Unfortunately, conventional techniques typically result in accessibility to the electrical contact structures in a first dimension (such as a vertical dimension), but access from a second dimension (such as a horizontal dimension) may be obscured. Accordingly, establishing bond wire connections that satisfy spacing and clearance requirements in stacked multi-chip configurations can be difficult.